; Copyright (C) 2015-2025 Intel Corporation
; SPDX-License-Identifier: BSD-3-Clause
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
;  * Redistributions of source code must retain the above copyright notice,
;    this list of conditions and the following disclaimer.
;  * Redistributions in binary form must reproduce the above copyright notice,
;    this list of conditions and the following disclaimer in the documentation
;    and/or other materials provided with the distribution.
;  * Neither the name of Intel Corporation nor the names of its contributors
;    may be used to endorse or promote products derived from this software
;    without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.

; SKD022: VM Entry That Clears TraceEn May Generate a FUP.
;
;         If VM entry clears Intel(R) PT (Intel Processor Trace)
;         IA32_RTIT_CTL.TraceEn (MSR 570H, bit 0) while PacketEn is 1 then a
;         FUP (Flow Update Packet) will precede the TIP.PGD (Target IP Packet,
;         Packet Generation Disable).  VM entry can clear TraceEn if the
;         VM-entry MSR-load area includes an entry for the IA32_RTIT_CTL MSR.
;
;   cpu 6/78
;   cpu 6/85
;   cpu 6/94
;   cpu 6/142
;   cpu 6/158
;   cpu 6/102
;   cpu 6/125
;   cpu 6/126
;   cpu 6/165
;   cpu 6/166
;   cpu 6/106
;   cpu 6/108
;   cpu 6/143
;   cpu 6/140
;   cpu 6/141
;   cpu 6/167
;   cpu 6/168
;   cpu 6/151
;   cpu 6/154
;   cpu 6/191
;   cpu 6/173
;   cpu 6/174
;   cpu 6/183
;   cpu 6/181
;   cpu 6/170
;   cpu 6/172
;   cpu 6/207
;   cpu 6/186
;   cpu 6/204
;   cpu 6/189
;   cpu 6/197
;   cpu 6/198
;   cpu 19/1
;   cpu 18/1
;   cpu 18/3
;   cpu 6/213
;

org 0x1000
bits 64

; @pt p0: psb()
; @pt p1: mode.exec(64bit)
; @pt p2: fup(3: %l0)
; @pt p3: psbend()
l0: vmlaunch

; @pt p4: fup(1: %l0)
; @pt p5: tip.pgd(0: %l1)
l1: hlt

; @pt p6: tip.pge(3: %l2)
l2: nop

; @pt p7: fup(1: %l3)
; @pt p8: tip.pgd(0: %l4)
l3: vmresume
l4: hlt


; @pt .exp(ptdump)
;%0p0  psb
;%0p1  mode.exec  cs.l
;%0p2  fup        3: %?l0
;%0p3  psbend
;%0p4  fup        1: %?l0.2
;%0p5  tip.pgd    0: %?l1.0
;%0p6  tip.pge    3: %?l2
;%0p7  fup        1: %?l3.2
;%0p8  tip.pgd    0: %?l4.0


; @pt .exp(ptxed)
;%0l0 # vmlaunch
;[disabled]
;[enabled]
;%0l2 # nop
;%0l3 # vmresume
;[disabled]
