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; Test that an INT followed by an IRET are decoded correctly.
;
; Variant: event tracing enabled
;          test that CVE.IRET could be bound to the IRET instruction (artificial)
;

org 0x100000
bits 64

; @pt p0: psb()
; @pt p1: fup(3: %l0)
; @pt p2: mode.exec(64bit, if)
; @pt p3: psbend()
l0: nop

; @pt p4: evd(0: 0xf00baa)
; @pt p5: cfe(1: 14)
; @pt p6: fup(1: %l1)
; @pt p7: tip(3: %l5)
; ...
; @pt p8: cfe(2)
; @pt p9: tip(3: %l1)
l1: mov rax, [rbx]

; @pt p10: cfe(14: 0x80)
; @pt p11: fup(1: %l2)
; @pt p12: tip(3: %l7)
; ...
; @pt p13: cfe(2)
; @pt p14: tip(3: %l3)
l2: int 0x80
l3: nop

; @pt p15: fup(1: %l4)
; @pt p16: tip.pgd(0: %l4)
l4: hlt

l5: iret
l6: hlt

l7: iret
l8: hlt


; @pt .exp(ptdump)
;%0p0  psb
;%0p1  fup        3: %0l0
;%0p2  mode.exec  cs.l, if
;%0p3  psbend
;%0p4  evd        0: f00baa     type cr2
;%0p5  cfe        1: 14         type intr
;%0p6  fup        1: %?l1.2
;%0p7  tip        3: %?l5
;%0p8  cfe        2             type iret
;%0p9  tip        3: %?l1
;%0p10 cfe        14: 128       type swintr
;%0p11 fup        1: %?l2.2
;%0p12 tip        3: %?l7
;%0p13 cfe        2             type iret
;%0p14 tip        3: %?l3
;%0p15 fup        1: %?l4.2
;%0p16 tip.pgd    0: %?l4.0


; @pt .exp(ptxed)
;%0l0                                   # nop
;[interrupt 14, cr2: 0000000000f00baa]  # mov rax, [rbx]
;[interrupt]
;%0l5
;[iret]
;%0l1                                   # mov rax, [rbx]
;[swintr 128]                           # int 0x80
;[interrupt]
;%0l7
;[iret]
;%0l3                                   # nop
;[disabled]
