       hw-interrupt-mep (libmepfamily.la :: mepfamily_component_library)

Synopsis:

   This component simulates the Toshiba Media Engine (MeP) interrupt
   controller unit.

     ----------------------------------------------------------------------

Functionality:

  Modelling:

   The interrupt controller model features a configurable number of (up to
   32) general purpose interrupts.

   The component models both edge and level triggered interrupts. When an
   interrupt source is configured as level triggered, an interrupt source pin
   repeatedly driving the same value will only constitute a single interrupt
   event.

   +-------------------------------------------------+
   |                    Behaviors                    |
   |-------------------------------------------------|
   |      reset | When the reset input pin is        |
   |            | driven, this component is reset to |
   |            | the hardware's normal power-up     |
   |            | state.                             |
   |------------+------------------------------------|
   |   register | When the registers bus is          |
   |     access | accessed, the appropriate 32-bit   |
   |            | control register is read or        |
   |            | written.                           |
   |            |                                    |
   |            | +-------------------------+        |
   |            | | byte address | register |        |
   |            | |--------------+----------|        |
   |            | | 0x0          | IVR      |        |
   |            | |--------------+----------|        |
   |            | | 0x4          | ISR      |        |
   |            | |--------------+----------|        |
   |            | | 0x8          | IER      |        |
   |            | |--------------+----------|        |
   |            | | 0xC          | IET      |        |
   |            | |--------------+----------|        |
   |            | | 0x10         | ILR0     |        |
   |            | |--------------+----------|        |
   |            | | 0x14         | ILR1     |        |
   |            | |--------------+----------|        |
   |            | | 0x18         | ILR2     |        |
   |            | |--------------+----------|        |
   |            | | 0x1C         | ILR3     |        |
   |            | +-------------------------+        |
   |------------+------------------------------------|
   |  interrupt | When any interrupt source is       |
   | processing | signalled, or interrupt-enabled    |
   |            | masks are modified, pending        |
   |            | interrupts are processed. Subject  |
   |            | to the then-current                |
   |            | interrupt-enabling registers, the  |
   |            | interrupt output pin may be driven |
   |            | with a value representing the      |
   |            | interrupt channel that was chosen. |
   |            |                                    |
   |            | The polarity for the input source  |
   |            | pins are positive, meaning that    |
   |            | non-zero values are interpreted as |
   |            | asserted.                          |
   |            |                                    |
   |            | Similarly named attributes may be  |
   |            | used to generate/monitor pin       |
   |            | traffic.                           |
   +-------------------------------------------------+

   +-------------------------------------------------+
   |                 SID Conventions                 |
   |-------------------------------------------------|
   | functional | supported | This is a functional   |
   |            |           | component.             |
   +-------------------------------------------------+

     ----------------------------------------------------------------------

Environment:

   Related components

   The interrupt controller typically sits between a CPU component, which
   usually has only one interrupt pin, and an array of other peripheral
   components. Each of the peripheral components is capable of generating its
   own interrupt. The following configuration file fragment demonstrates how
   to connect two simple timers into the interrupt subsystem of a more
   complete simulation:

         new hw-cpu-mep cpu
         new hw-timer-arm/ref-nosched timer1
         new hw-timer-arm/ref-nosched timer2
         new hw-interrupt-mep intc
         connect-pin timer1 interrupt -> intc interrupt-source-0
         connect-pin timer2 interrupt -> intc interrupt-source-1
         connect-pin intc interrupt -> cpu irq

     ----------------------------------------------------------------------

Component Reference:

  Component: hw-interrupt-mep

   +--------------------------------------------------------+
   |                          pins                          |
   |--------------------------------------------------------|
   |         name          |direction|legalvalues|behaviors |
   |-----------------------+---------+-----------+----------|
   |reset                  |in       |any        |reset     |
   |-----------------------+---------+-----------+----------|
   |interrupt-source-[0,31]|in       |any        |interrupt |
   |                       |         |           |processing|
   |-----------------------+---------+-----------+----------|
   |                       |         |-1         |          |
   |interrupt              |out      |(inactive) |interrupt |
   |                       |         |or [0,31]  |processing|
   |                       |         |(active)   |          |
   +--------------------------------------------------------+

   +-------------------------------------------------+
   |                      buses                      |
   |-------------------------------------------------|
   |   name    | addresses |  accesses  | behaviors  |
   |-----------+-----------+------------+------------|
   | registers | 0x0--0x1C | read/write | register   |
   |           |           |            | access     |
   +-------------------------------------------------+

   +------------------------------------------------------------------------+
   |                               attributes                               |
   |------------------------------------------------------------------------|
   |             name              |category |  legal   |default|behaviors ||
   |                               |         |  values  | value |          ||
   |-------------------------------+---------+----------+-------+----------||
   |reset                          |pin      |any       |-      |reset     ||
   |-------------------------------+---------+----------+-------+----------||
   |interrupt                      |pin      |-1,       |-      |interrupt ||
   |                               |         |[0..31]   |       |processing||
   |-------------------------------+---------+----------+-------+----------||
   |interrupt-level                |read-only|[1,3,7,15]|-      |interrupt ||
   |                               |register |          |       |processing||
   |-------------------------------+---------+----------+-------+----------||
   |interrupt-mask-level           |register |[1,3,7,15]|-      |interrupt ||
   |                               |         |          |       |processing||
   |-------------------------------+---------+----------+-------+----------||
   |interrupt-channel-number       |read-only|[0..31]   |-      |interrupt ||
   |                               |register |          |       |processing||
   |-------------------------------+---------+----------+-------+----------||
   |interrupt-status-register      |read-only|any       |-      |interrupt ||
   |                               |register |          |       |processing||
   |-------------------------------+---------+----------+-------+----------||
   |interrupt-enable-register      |read-only|any       |-      |interrupt ||
   |                               |register |          |       |processing||
   |-------------------------------+---------+----------+-------+----------||
   |interrupt-edge-trigger-register|read-only|any       |-      |interrupt ||
   |                               |register |          |       |processing||
   |-------------------------------+---------+----------+-------+----------||
   |interrupt-level-register-0     |read-only|any       |-      |interrupt ||
   |                               |register |          |       |processing||
   |-------------------------------+---------+----------+-------+----------||
   |interrupt-level-register-1     |read-only|any       |-      |interrupt ||
   |                               |register |          |       |processing||
   |-------------------------------+---------+----------+-------+----------||
   |interrupt-level-register-2     |read-only|any       |-      |interrupt ||
   |                               |register |          |       |processing||
   |-------------------------------+---------+----------+-------+----------||
   |interrupt-level-register-3     |read-only|any       |-      |interrupt ||
   |                               |register |          |       |processing||
   |-------------------------------+---------+----------+-------+----------||
   |interrupt-name-[0,31]          |setting  |any       |-      |          ||
   +------------------------------------------------------------------------+

  Variant: hw-interrupt-mep-1

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-2

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-3

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-4

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-5

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-6

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-7

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-8

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-9

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-10

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-11

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-12

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-13

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-14

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-15

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-16

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-17

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-18

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-19

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-20

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-21

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-22

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-23

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-24

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-25

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-26

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-27

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-28

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-29

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-30

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-31

   Same as hw-interrupt-mep

  Variant: hw-interrupt-mep-32

   Same as hw-interrupt-mep
