Index: llvm/lib/Target/Mips/MipsISelLowering.cpp
--- llvm/lib/Target/Mips/MipsISelLowering.cpp.orig
+++ llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -4025,6 +4025,7 @@ MipsTargetLowering::getConstraintType(StringRef Constr
   //       backwards compatibility.
   // 'c' : A register suitable for use in an indirect
   //       jump. This will always be $25 for -mabicalls.
+  // 'h' : The hi register. 1 word storage.
   // 'l' : The lo register. 1 word storage.
   // 'x' : The hilo register pair. Double word storage.
   if (Constraint.size() == 1) {
@@ -4034,6 +4035,7 @@ MipsTargetLowering::getConstraintType(StringRef Constr
       case 'y':
       case 'f':
       case 'c':
+      case 'h':
       case 'l':
       case 'x':
         return C_RegisterClass;
@@ -4079,6 +4081,7 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
       weight = CW_Register;
     break;
   case 'c': // $25 for indirect jumps
+  case 'h': // hi register
   case 'l': // lo register
   case 'x': // hilo register pair
     if (type->isIntegerTy())
@@ -4257,6 +4260,11 @@ MipsTargetLowering::getRegForInlineAsmConstraint(const
         return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
       // This will generate an error message
       return std::make_pair(0U, nullptr);
+    case 'h': // use the `hi` register to store values
+              // that are no bigger than a word
+      if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
+        return std::make_pair((unsigned)Mips::HI0, &Mips::HI32RegClass);
+      return std::make_pair((unsigned)Mips::HI0_64, &Mips::HI64RegClass);
     case 'l': // use the `lo` register to store values
               // that are no bigger than a word
       if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
